Glossary

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Access Breakpoints

Access Breakpoints are Hardware Breakpoints that are configured to stop the CPU execution after a specific value was written to / read from the memory.



BDM

Background Debug Mode

Read about it on Wikipedia.


DWT

Data Watchpoint and Trace unit

The DWT is an optional debug unit for Cortex-M that provides watchpoints, data tracing, and system profiling for the processor.


ELF

Executable and Linkable Format

Read about it on Wikipedia


ETM

Embedded Trace Macrocell

Read about it on ARM website.


Execution Breakpoints

Execution Breakpoints are typically pre-execution breakpoints that stop the CPU before an instruction on the address with the breakpoint set on it is executed. Execution Breakpoints can be applied as Hardware Breakpoints (on-chip / emulator debug logic is used to set the breakpoint) or Software Breakpoints (an instruction that stops the CPU execution replaces the original instruction).



GDB

GNU Project debugger

Read about it on GDB website.


HIL

Hardware in the Loop

Read about it on Wikipedia


ICE

In-Circuit Emulation

In this emulation mode, the CPU on the target board is replaced by an emulation POD. The POD hosts the same CPU or a special emulation version of it. All CPU buses are visible to the emulator and very detailed control or observation of the CPU is possible.


This technology is used for slow CPUs up to 30MHz system clock.


JTAG

Joint Test Action Group

Read about it on Wikipedia


MMU

Memory Management Unit

Read about it on Wikipedia


OCD

On Chip Debug

Most modern CPUs implement a debug module on the device itself. The debug module can access the device memory and registers, stop, step and run the core, etc.


The debugger hardware communicates to the OCD module via a serial protocol, like JTAG.


OCT

On Chip Trace

If a CPU is too fast to be emulated using an ICE, OCD is used. This however obscures the real-time flow (program execution, data accesses) of the application. Some CPUs provide a trace module on the device, which compresses the CPU activities and transmits them to the debugger hardware via a high speed parallel protocol (like Nexus or ETM), or a serial protocol (like Aurora).


Typically the program trace, which is highly compressible, can be sustained indefinitely. Data trace however must be explicitly limited to observation of a few locations only.


If the amount of generated trace data is bigger than the bandwidth of the trace port, the trace will either stop, the CPU can be (optionally) stalled, or the reconstructed trace stream will have gaps.


OCTB

On Chip Trace Buffer

Big System-On-Chip devices operating in GHz range are too fast even for high speed trace ports. To provide some kind of trace functionality, the device provides a dedicated RAM where the compressed stream of CPU activity is stored. Depending on device, the RAM buffer can range from a few Bytes up to 1MB.


A very simple OCD debugger can then access this data via standard OCD port (JTAG).


The biggest drawback of OCTB is that the amount of recorded data is inherently limited and thus only short trace session are possible.


RTOS

Real-time Operating System

Read about it on Wikipedia.


RTR

Real-time Trace Reconstruction

A compressed OCT stream must be decompressed to obtain real CPU activity again. This is typically done on the host PC – offline. If however some activity must be acted upon in real-time, a very high-end emulator can decompress the OCT stream in real-time. This way a program execution of a specific function or write to a specific variable, can be converted into a physical signal which can trigger other equipment, like oscilloscopes or HIL systems.


SFR

Special Function Register

Read about it on Wikipedia.


SoC

System on a Chip

System on a Chip is an integrated circuit that contains all components of a computer in a single chip. Typically it contains one or more CPUs and peripherals such as debug module, trace module, timers, analog-digital converters... Read more about it on Wikipedia.


VLE

Variable Length Encoding

This is an alternate instruction set on the e200 Power Architecture CPUs. It uses combinations of 16 and 32-bit instructions to reduce the overall size of the program code.