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This document is intended to be used together with the CPU reference manual provided by the silicon vendor. This document assumes knowledge of the CPU functionality and the terminology and concepts defined and explained in the CPU reference manual. Basic knowledge of winIDEA is also necessary. This document deals with specifics and advanced details and it is not meant as a basic or introductory text.


Contents        1

1        Introduction        2

2        Emulation Options        3

2.1        Hardware Options        3

2.2        CPU Configuration        4

2.3        Clock Source        5

2.4        Initialization Sequence        6

3        Setting CPU options        6

3.1        Reset        6

3.2        Advanced Options        7

3.3        Mapping Select 0        7

3.4        Mapping Select 1        9

4        Memory Access        9

5        Access Breakpoints        10

6        Emulation Notes        11

6.1        Miscellaneous        11

7        Trace        11

8        Profiler        11

9        Coverage        11


Internally, this development system features the FPGA based module emulating the CPU core and a so called AS module, which was designed by EM Microelectronic and allows them implementing different peripherals.

Debug Features

Unlimited breakpoints

Access breakpoints

Real-time access



2Emulation Options

2.1Hardware Options

Active Emulator Options dialog, Hardware page

Clear Emulation Memory

This option allows you to force clearing (with the specified value) of emulation memory after the emulation unit is initialized.

2.2CPU Configuration

With In-Circuit emulation besides the CPU family and CPU type the emulation POD must be specified (some CPU's can be emulated with different PODs).

Active Emulator Options dialog, CPU Configuration page

CPU Setup

Opens the CPU Setup dialog. In this dialog, parameters like memory mapping, bank switching and advanced operation options are configured. The dialog will look different for each CPU reflecting the options available for it.

Set Default

This button will set default options for currently selected CPU. These include:

Vcc and clock source and frequency

Advanced CPU specific options

Memory configuration (debug areas, banks, memory mapping)

Note: Default options are also set when the Family or a POD is changed.

2.3Clock Source

The Vcc/Clock Setup page determines the CPU's clock source.

In-Circuit Emulator Options dialog, Vcc/Clock Setup page

Clock Source

Note: This configuration is not available when “CR816L Rev 2” CPU is selected

Clock source can be either used internal from the emulator or external from the target. It is recommended to use the internal clock if possible.

When using the clock from the target, it can happen that the emulator fails to initialize. In this case, the corresponding line is routed directly from the target system to the emulated CPU on the POD.

It is dissuaded to use a crystal in the target as an external clock source during the emulation.  It is recommended that the oscillator is used instead. Normally, a crystal and two capacitors are connected to the CPU's clock inputs in the target application as stated in the CPU datasheet. A length of clock paths is critical and must be taken into consideration when designing the target. During the emulation, the distance between the crystal in the target and the CPU (on the POD) is further more increased; therefore the impedance may change in a manner that the crystal doesn't oscillate anymore. In such case, a standalone crystal circuit, oscillating already without the CPU must be built or an oscillator must be used.

When the clock source is set to Internal, the clock is provided by the emulator and its frequency can be set in steps of 1 kHz.

Note: The clock frequency is the frequency of the signal on the CPU's clock input pin. Any internal manipulation of it (division or multiplication) depends entirely on the emulated CPU.

2.4Initialization Sequence

Usually, there is no need to use initialization sequence when debugging with an In-Circuit Emulator (ICE) a single chip application. Primarily, initialization sequence is used on On-Chip Debug systems to initialize the CPU after reset to be able to download the code to the target (CPU or CPU external) memory. With an ICE system, the initialization sequence may be required for instance to enable memory access to the CPU internal EEPROM or to some external target memory, which is not accessible by default after the CPU reset. The user can also disable CPU internal COP using initialization sequence if there is a need for that, etc.

Initialization sequence is executed immediately after the CPU reset and then the code is downloaded.  Detailed information may be found in the Initialization Sequence help topic.

3 Setting CPU options


CPU Setup, Options page

RESET from Target Enabled

When checked, the target reset line is sensed and the development system is reset upon active reset state occurrence.

3.2Advanced Options

Advanced Options

AS Firmware

This development system can be used for different projects using CPUs with different peripheral sets since the AS module can emulate different peripherals by downloading a different firmware (provided by EM Microelectronic) into the FPGA inside the development system.

Note that the AS firmware is loaded serially. Therefore, through this option it’s possible to program multiple FPGAs when there are other FPGAs in the target connected in the chain with the FPGA on the AS module.

AS firmware name and location are defined by winIDEA installation path.

CPU firmware

While primarily it’s meant for the CPU core firmware to be loaded from winIDEA internal resources, it is also possible to load custom CPU firmware.

CPU firmware name and location are defined by winIDEA installation path.

3.3Mapping Select 0

This page configures the mode of the on-chip memory expansion unit. It is shown only for CPUs with integrated memory expansion unit.

Memory Expansion

Memory Expansion Enabled

If Memory Expansion is being used, this option must be checked. According to this selection, the mapping on the POD is automatically configured.

3.4Mapping Select 1

This page configures the mode of the on-chip memory expansion unit. It is shown only for CPUs with integrated memory expansion unit.

4Memory Access

CoolRISC development system features only standard monitor memory access, which requires user program to be stopped.

Real-Time Memory Access

Real-time memory access is not supported.

Monitor Access

When monitor access to the CPU’s memory is requested, the emulator stops the CPU and instructs it to read the requested number of bytes.

Since all accesses are performed using the CPU, all memory available to the CPU can be accessed. The drawback to this method is that memory cannot be accessed while the CPU is running. Stopping the CPU, then accessing the memory and resuming the application is an option, which however, affects the real time execution considerably.

The time the CPU is stopped for is relative and cannot be exactly determined. The software has full control over it. It stops the CPU, updates all required windows and sets the CPU back to running. Therefore the time depends on the communication type used, PC's frequency, CPU's clock, number of updated memory locations (memory window, SFR window, watches, variables window), etc.

5Access Breakpoints

Access breakpoints dialog is open by clicking the ‘Hardware breakpoints’ button in the Breakpoints dialog.


Press the ‘New…’ button to configure new breakpoint.

Access breakpoint can be set on a single address or on a range.


The trigger condition can be also combined with a counter (Pass Count) and a valid C expression can be also specified to be evaluated at the trigger address match. When ‘High Level’ option is checked, the tool will evaluate the condition when the next source line is reached. If unchecked, the evaluation will be performed immediately.

When a breakpoint occurs, two actions can be selected in the Action page.

6Emulation Notes


Remove all emulator breakpoints when performing any kind of checksum since they may impact the checksum result.


CoolRISC development system features a powerful trace named Bus Trace, which is implemented externally to the CPU.

For more information on these trace functionalities and use refer to winIDEA Contents Help describing Bus Trace in details.

Note: Data qualifiers and data trigger events can be configured with some restrictions. A single address and data item can be configured for events A, B, C and Q in the trace Trigger and Qualifier configuration dialog. This applies for Secondary (Data) Bus only. Primary (Program) Bus has no restrictions and allows configuring unlimited number of address and data items when configuring A, B, C and Q events.


Refer to winIDEA Contents Help, Profiler Concepts section for Profiler theory and background.

Refer to winIDEA Contents Help, Analyzer Window section (or alternatively to the standalone Analyzer.pdf document) for information on Profiler user interface and use.

Note: Up to 4 data access ranges can be profiled with the Data profiler and an unlimited number of code objects can be profiled with the Code profiler.


Coverage functionality is not supported on CoolRISC development system.

Disclaimer: iSYSTEM assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information herein.

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