Initialization Sequence

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75Introduction

An embedded application must itself properly initialize the CPU and surrounding components to be able to run correctly. There are however situations during development and production when it is beneficial to condition the system before the application runs.

These are some typical situations:

Configuration of chip-select logic to allow download into memory devices not accessible after CPU is reset

Configuration of system clock to allow faster JTAG clock operation, download, etc.

Disabling of watchdog timers

Important: Be aware that the initialization is only used with debugger attached. When the target is running standalone, the initialization is not performed and the target can behave differently.

75.1Initialization Execution

winIDEA can execute initialization at these events:

75.1.1After CPU emulation is started and CPU stops on reset position.

At this point the initialization is typically used to prepare the system for download.

This initialization can be invalidated after download completes (the CPU is reset again). This way the CPU starts in a ‘standalone mode’, but with a programmed memory.

Note: CPUs that cannot be stopped immediately after reset is released (e.g. HC12/HCS12 through the on-chip debug module), are not initialized until they are stopped. Refer to the separate technical notes that came with your system for more information.

75.1.2After program download completes.

Initialization at this point is used when the main initialization is invalidated by a CPU reset after download, but some initialization is still required.

76Configuration

CPU initialization is configured in Hardware/Emulation Options dialog.

The Initialization tab configures initialization at the point where CPU emulation is first started and before download is performed.

The Initialization After Download tab configures initialization after program download is complete.

The most common configuration is depicted above: Init sequence loaded from an external initialization file.

The initialization file is best created by duplicating the sequence of system initialization from the application boot code.

Initialization

The Initialization option defines the action to take when initializing the CPU.

none – no initialization is performed

Init sequence – the initialization sequence as defined in the initialization file is performed

Reset target, Run... – the target is reset and the CPU is set to running for the specified number of seconds. This option is used if the system already has a bootstraper programmed. By allowing the bootstraper to run for a few seconds, the essential initialization is performed.

Reset, Run…, Init. seq. – the target is reset, the CPU is set to running for the specified number of seconds and the initialization sequence is performed.
This option combines the initialization of the bootstraper and some additional initialization.

Load from file

If this option is checked, the initialization is loaded from an external file. winIDEA can read these file types:

winIDEA format (.ini)

Freescale CodeWarrior format (*.mac)

Note: to facilitate debugging any issues, winIDEA creates a converted winIDEA initialization (.ini) file next to the .mac file. The file is named $mac_file_name.ini

Address offset

The memory initialization offset can be either read from the CPU (select the ‘Read from CPU’ option) or specified manually (select the ‘Specify’ option). The memory initialization offset is usually the offset of the register base.

The value specified here (or established from CPU base) is added to the initialization items which are specified as relative to this base.

Reset CPU after DL/reset commands

If this option is checked, the CPU is reset after download completes. This effectively invalidates the initialization (which was used to allow download) and provides the CPU with an environment equal to standalone operation (without debugger attached).

Note: this option is only available in the Initialization tab.

76.1Specifying Initialization Items Interactively

For all initializations using an initialization file is recommended. If however only a few simple items are required, interactive configuration can be used.

Configuration is performed in the bottom part of the dialog using Add, Remove and Properties buttons.

Write To

Specifies the address to write to. This can be either:

A memory mapped register; to specify a memory mapped register, first specify the memory area, then you can specify either a

Hexadecimal value. If the value matches a SFR, its name is displayed below

A SFR register name. If recognized, its hexadecimal value and the memory area of the SFR is displayed above.
Most commonly used SFRs are available in the drop down box.

Note: The address offset, specified in the ‘Initialization’ dialog will be used, if Use address offset is checked

A CPU Core register. To specify a CPU core register, select it from a drop down box.

Data

Can be set to either an 8-bit (Byte), a 16-bit (Word) or a 32-bit (Long) write.

Value can be specified either as a hexadecimal number in the edit box, or as a mask. In either case both fields reflect current setting.

77winIDEA Initialization File Format

winIDEA initialization files use plain text format. An initialization item is defined in a single line.

The syntax is case-insensitive, which means that, for example, either #define or #DEFINE is considered the same.

No arithmetic is supported. These expressions are illegal:

#define ABC 0x000FFFFF+1

#define ABC PREV_EXP+1

77.1Preprocessor

C-like pre-processor is used.

77.1.1Aliases

#define <alias> <value>

Example:

#define SP Supervisor

#define ALL_ONES 0xFFFFFFFF

#define ALL_ZERO 0x00000000

77.1.2Comments

Multiline comments

Standard C /*  */ multi-line comments are supported.

Example:

/* this is a begin of a multi-line comment

This is the end */

End of line comments

Double forward-slash characters are interpreted as end of line comments.

Example:

#define SP Supervisor // this is a comment

77.1.3Tokens with Spaces

If a token contains a space, it must be enclosed in double quotes.

Example:

#define SP “Supervisor Data” // memory space name contains a whitespace and must be enclosed in quotes

77.2Item Types

Write Item

A write item causes a target location to be written.

Syntax:

<destination> [memory area:]<address> <size> <data> [number of repeats]

<destination> = S | A | R

 S        memory location, address offset is used

 A        memory location, absolute addresses

 R        core register

[memory area:]

Memory area specifies the name of the CPU’s memory space where the write is performed.

The string specifying the area is CPU specific. For applicable values see end of this section.

This parameter is optional. If omitted, the default SFR memory space is used.

<address> = <literal> | <register name>

 <literal> = C number syntax literal

 <register name> = name of the register as displayed in the SFR window

<size> = B | W | L

 B        8-bit width

 W        16-bit width

 L        32-bit width

<data> = C number syntax literal

[number of repeats]

Number of repeats is an optional parameter used for block writes, which specifies the number of times the data is written.

Note: L size data repeated 5 times, writes 20 bytes.

Examples:


S DEC L 0xFFFFFFFF                // initialize DEC register

S 0x40000000 L 0x0 0x4000        // write 16k * 32-bit = 64kB of zeros

R R3 L 0x12345678                // store 0x12345678 in the R3 core register

Modify Item

A modify item reads the memory location specified by the <address> and <size>, modifies the bits specified by <mask> to a <data> value and writes the modified value back to the same memory location.

Syntax:

M [memory area:]<address> <size> <mask> <value>

Where:

[memory area:]

Memory area specifies the name of the CPU’s memory space where the write is performed.

The string specifying the area is CPU specific. For applicable values see end of this section.

This parameter is optional. If omitted, the default SFR memory space is used.

<address> = <literal> | <register name>

 <literal> = Hexadecimal value prefixed with 0x

 <register name> = name of the register as displayed in the SFR window

<size> = B | W | L

 B        8-bit width

 W        16-bit width

 L        32-bit width

<mask> = Hexadecimal value prefixed with 0x, only set bits will be modified

<data> = Hexadecimal value prefixed with 0x

Example:

M 0x200080C4 L 0x00000003 0x00000002

Modifies the last 2 bits of the 32-bit value at 0x200080C4 to b’10’.

Pause Item

Introduces a delay.

Syntax:

P <delay in ms>

Example:

P 100

Inserts a delay of 100ms.

Reset Item

Resets the CPU.

Syntax:

B

Instruction Item

Executes a CPU instruction. No inline assembler is supported – the op-code must be specified in HEX format.

Syntax:

I <op-code as HEX literal>

Example:

I 7C0007A4  // tlbwe

Executes the 7C0007A4 opcode.

Poll Item

Polls a memory location until a specified bit is set.

Syntax:

<source> [memory area:]<address> <size> <data> <mask> <timeout>

<source> = C | D

 C        memory location, address offset is used

 D        memory location, absolute addresses

[memory area:]

See Write Item.

<address>

See Write Item.

<size>

See Write Item.

<data>

See Write Item.

<mask>

Same format as <data>. winIDEA will repeat memory reads while:

(mem(address) & mask) != data


<timeout>

Time in milliseconds to wait for completion.

Example:

C 0xE01FC084 W 0x200F 0xF0FF 500

reads 16 bit words from address E01FC084 for 500 ms, or until the read value is 2x0F

Copy Item

Reads value from some address and writes it to some other address.

Syntax:

X [memory area:]<source address> <size> [memory area:]<destination address>

[memory area:]

See Write Item.        

<source address> <destination address>

See  Write Item <address>.

<size>

See Write Item.


77.3Memory Spaces

These architectures support multiple memory spaces. On other architectures (not listed below) the memory space can be omitted.

CPU

Memory Areas

8051

CODE             BankIDATA

DATA             EDATA  

IDATA            HDATA  

BDATA            EEPROM  

XDATA            PHYSICAL

PDATA            SFR    

196

CODE             REGISTER

DATA    

251

Physical         IDATA  

Register         BDATA  

SFR              XDATA  

CODE             PDATA  

DATA             DATAB  

Z180

Physical         Logical

IO    

Z80, 8085, x86

Physical         IO    

HC12/HCS12/S12X

Logical          Linear

Bank  

HC16

Data             Program

68k

Program          Supervisor Program

Data             Supervisor Data                

User Program     CPU Space        

User Data        

XC166/XC2000

Physical         BDATA  

Logical

TriCore

Physical  

Virtual

MCORE

Physical         User      

Supervisor

PowerPC

Virtual          SPR    

Physical         DCR    

TLB    

ARM

Physical         Coprocessor

Virtual  

CoolRISC

Program          AS ID

Data  

V850

Physical         Host    

ARC

Physical         AUX Regs

78k

Physical         ER      



Disclaimer: iSYSTEM assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information herein.

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