Cortex-based CPUs can contain none, one or more on-chip trace units which can all simultaneously be active and generate trace output. Some significant changes were introduced to the system architecture to allow for multiple trace streams to be output and captured. Cortex CPUs internally implement CoreSight component architecture which provides a way to output multiple trace streams over a single trace port.
Cortex-based CPUs can come equipped with no, one or more trace modules of different types:
ITM - Instrumentation Trace Macrocell (software instrumentation)
DWT - Data Watchpoint and Trace (DWT hardware event trace)
ETM - Embedded Trace Macrocell (instruction and/or data trace)
PTM - Program Trace Macrocell (instruction trace)
HTM - AMBA AHB Trace Macrocell (address and data trace of AHB bus)
ITM and DWT are common on Cortex-M CPUs but not on Cortex-R or Cortex-A profiles. ITM provides “printf”-like trace ability using stimulus ports (memory mapped) to which target application can perform memory writes whose information is then output in a form of a trace packet in the ITM/DWT trace stream. DWT provides a low bandwidth focused data trace using comparators to detect memory accesses and then generate trace packets with information about memory accesses.
ETM trace module comes in a couple of versions. Cortex-M ETM variants usually don’t feature data trace and own comparators. Cortex A/R ETM is usually fully featured.
PTM is mostly implemented on high performance Cortex-A devices.
HTM is an AMBA bus trace cell which can be found on some higher-end Cortex-M based CPUs. HTM provides full data trace capability to complement the Cortex-M ETM which offers only program flow trace.
Each of different trace units also incorporates its own triggering system which can make for a quite complex trigger configuration on CPUs with multiple trace units on-board.
All trace sources on Cortex based CPUs output trace information in a byte oriented stream protocol and this is the key factor that allows multiple trace sources to be output over a single trace port in a merged trace stream which is then recorded by iSYSTEM trace hardware.
ETM is a trace source component which outputs information stream about program execution and data accesses. It is common to all Cortex profiles (A, R and M).
winIDEA provides a dialog for ETM component configuration within Analyzer trigger configuration:
Dialog is made per ETM architecture specification. Note that specific ETM implementation defines the available functionality and resources. Consult specific ETM implementation documentation for detailed information about available functionality and resources. In winIDEA the parts that are not available on ETM for selected CPU are disabled and cannot be configured in dialog.
Use ‘Wizard…’ for easier configuration of common trace scenarios.
Example of ETM output stream in Trace window
ETMv4 is a newer version of Embedded Trace Macrocell architecture.
The ETMv4 architecture introduces the following changes from previous trace architectures from ARM:
• It supports addresses up to 64 bits wide.
• It supports the ARMv8 architecture.
• In addition to instruction tracing, it provides optional support for:
•Tracing of conditional non-branch instructions.
• It provides better compression than previous trace architectures from ARM.
Dialog is made per ETMv4 architecture specification. As for previous version of ETM, implementation defines the available functionality and resources. Consult specific ETM implementation documentation and device reference manual for detailed information about available functionality and resources. In winIDEA the parts that are not available on ETMv4 for selected CPU are disabled and cannot be configured in dialog.
Use ‘Wizard…’ for easier configuration of common trace scenarios.
Example of ETMv4 output stream in Trace window
Newer Cortex A devices features PTM instead of ETM. winIDEA trace configuration dialog provides a dialog for PTM component configuration. Note that PTM doesn’t feature data trace capabilities.
Parts of dialog are disabled according to the capabilities of selected CPU.
ITM module enables software instrumentation in the target application (same concept as with printf). Software instrumentation is performed by the target application writing application specific values into a series of ITM stimulus port registers which cause trace messages to be output over the trace port. winIDEA displays ITM output either in Trace window or terminal window. ITM with DWT is usually featured on Cortex-M devices.
ITM terminal example usage and configuration
In Trace window the stimulus register ID is shown in Address column and data written to it in Data column.
ITM results in the trace window
ITM module configuration is combined in a dialog with DWT configuration (see Data Watchpoint and Trace for more information).
DWT module provides means for generating various hardware trace events which are user configurable like hardware access breakpoints (see Access Breakpoints for more information). This is due to the same hardware comparators used for hardware access breakpoints and trace event generation.
Note: If DWT hardware comparators are used for access breakpoint operation, then they cannot be used for trace event generation at the same time.
DWT with ITM is usually featured on Cortex-M devices.
winIDEA provides a dialog for DWT configuration. It is combined with ITM configuration because the two modules are usaully featured together. Not all possible options might be configurable. The set of configurable options is defined by device implementation.
DWT hardware event generation and ITM configuration
Note that access type distinction (read, write, read or write) for the DWT comparators is not supported on every device. Consult device documentation for more information on explicit access distinction.
Check Enable ITM timestamps option to configure the CPU to generate ITM timestamp messages. Check Timestamp Source option to use ITM generated timestamps as main analyzer time source. This option is intended to be used together with on-chip trace buffer (OCTB / SWO trace), where timestamps would otherwise not be available. Do not enable this option when parallel trace is being used. When disabled, winIDEA will use the emulator's internal timestamp (which is only possible when parallel trace is being used). For more information check ARM reference manual.
DWT Trace and Profiler results
Micro Trace Buffer (MTB) is supported by some Cortex-M0+ microcontrollers and it provides basic execution trace functionality. It records changes in the CPU's program flow and saves recorded trace packets in the SRAM. Both the MTB and the CPU can access the SRAM, but MTB write operations have higher priority. A debugger can then access the trace records and reconstruct the program flow, which can be used for coverage analysis. Timestamps are not available, therefore the timing analysis is not possible.
Note: MTB does not offer any other trace capability other than execution trace.
By default the MTB runs in a cyclic mode, which means that once the buffer is full, the new trace information will overwrite the old trace information.
Prior to the first use the Micro Trace Buffer must be configured through the Hardware / CPU Options / SoC Advanced tab:
Buffer Size – Specify the size in kilobytes (kB).
Buffer Address – Specify the address in the SRAM where the trace information will be stored. When specifying the address make sure that:
-the application does not use this part of the memory
-the address is aligned to the buffer size (e.g. if the buffer size is 1kB, the buffer address must be aligned to 0x400 as well. This is necessary when the MTB works in the cyclic mode.
MTB configuration dialog
Micro Trace Buffer has a few more options available through the manual trigger / recorder configuration dialog:
Start Trace Immediately – Is a trace control options. Checking it enables trace immediately on CPU run. When this flag is unchecked, trace will need to be activated by triggering from MTB DWT module.
Stop trace when full – The trace recording will stop once the buffer is full. This option disables the MTB's cyclic mode.
Stop CPU when full – CPU (and the trace recording) will stop once the buffer is full. This option disables the MTB's cyclic mode.
Analyzer Configuration / Manual trigger/recorder configuration
The MTB_DWT is to generate TSTOP and TSTART signals of ARM Core-sight MTB. The MTB_DWT function monitors the processor address and data buses when accessing data phase, configurable watch points can be detected to trigger the appropriate response in the MTB recording.
Features of MTB_DWT
•Support addresses and address + data programmable start/stop recording.
•Support masking each bit of data.
•Support write/read and read or write operations monitor.
•Support byte, half-word and word monitor.
•Support data phase monitor function.
MTB DWT dialog is available through the manual trigger / recorder configuration dialog in Analyzer Configuration:
MTB DWT configuration overview
Depending on CPU implementation and configuration different number of comparators can be selected for use.
MTB DWT comparator configuration
Action – Select which trace trigger is generated on comparator match. This will start or stop MTB trace recording.
Linked with – A comparator can be linked with up to two other comparators to generate trigger signal based on data and address/address range comparison.
Note: winIDEA offers superset of configuration options. Not all options and combinations are necessarily available on all devices. Refer to your target device reference manual for available configuration.
Disclaimer: iSYSTEM assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information herein.
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