Description

Contains CPU family and variant.

#include <CCPUInfo.h>

Public Types
enum	ECPUFamily { cpu_8051 = 1 , cpu_RISCV = 2 , cpu_Xtensa = 3 , cpu_ARC = 4 , cpu_x86 = 5 , cpu_PowerPC = 18 , cpu_ARM = 22 , cpu_V850 = 25 , cpu_78k = 28 , cpu_TPU = 34 , cpu_TriCore = 37 , cpu_GTM = 40 , cpu_SPT = 42 , cpu_Num , cpu_Generic = 0xFFFF }
	Defines CPU Family IDs. More...

enum	E8051 { v8051_8051 , v8051_Num }
	Defines 8051 variants. More...

enum	EPowerPC { vPowerPC_4xx , vPowerPC_5xx , vPowerPC_6xx , vPowerPC_7xx , vPowerPC_8xx , vPowerPC_G5 , vPowerPC_G3 , vPowerPC_Num }
	Defines PowerPC variants. More...

enum	EARMVariant { vARM_v3 , vARM_v4T , vARM_v5TE , vARM_v5TEJ , vARM_v6 , vARM_v7A , vARM_v7R , vARM_v7M , vARM_v6M , vARM_v8A , vARM_v8R , vARM_v8M , vARM_Num }
	Defines ARM variants. More...

enum	EARMState { sARMv8_EL0 = 0x0000 , sARMv8_EL1 = 0x0001 , sARMv8_EL2 = 0x0002 , sARMv8_EL3 = 0x0003 , sARMv8_ELMask = 0x0003 , sARMv8_Secure = 0x0004 , sARMv7_PL0 = sARMv8_EL0 , sARMv7_PL1 = sARMv8_EL1 , sARMv7_PL2 = sARMv8_EL2 , sARMv7_ELMask = sARMv8_ELMask , sARMv7_Secure = sARMv8_Secure }
	Defines ARM states. More...

enum	EV850
	Defines V850 variants.

enum	ETriCore { vTriCore13 , vTriCore16 , vTriCore16E , vTriCore16P , vTriCore162P , vTriCore18 , vTriCore_Num }
	Defines Tricore variants. More...

enum	ERISCV { vRISCV_RV32I , vRISCV_RV32E , vRISCV_RV64I , vRISCV_RV128I , vRISCV_Num }
	Defines RISCV variants. More...

enum	EFeature_RISCV { fRISCV_M , fRISCV_A , fRISCV_F , fRISCV_D , fRISCV_Q , fRISCV_L , fRISCV_C , fRISCV_B , fRISCV_J , fRISCV_T , fRISCV_P , fRISCV_PULP , fRISCV_V , fRISCV_N , fRISCV_H , fRISCV_ZiCSR , fRISCV_Zifencei , fRISCV_Zam , fRISCV_Ztso , fRISCV_AndesPerformance , fRISCV_AndesCoDense , fRISCV_AndesINT4VectorLoad , fRISCV_AndesScalarBFLOAT16Conversion , fRISCV_AndesVectorBFLOAT16Conversion , fRISCV_AndesDSP }
	Defines RISCV features. More...

Public Member Functions
bool	IsFeature (int nFeature) const
	Returns true, if feature is present.

Public Attributes
uint16_t	m_wCPU = cpu_Generic
	Contains CPU family.

uint16_t	m_wVariant = 0
	Contains CPU variant ID.

uint16_t	m_wSubVariant = 0
	Contains CPU subvariant ID.

uint32_t	m_adwFeatures [MAX_FEATURES/32] {}
	used in parameterizable cores

Member Enumeration Documentation

◆ E8051

enum CCPUInfo::E8051

Defines 8051 variants.

Enumerator
v8051_8051	8051

◆ EARMState

enum CCPUInfo::EARMState

Defines ARM states.

Enumerator
sARMv8_EL0	v8
sARMv7_PL0	v7

◆ EARMVariant

enum CCPUInfo::EARMVariant

Defines ARM variants.

Enumerator
vARM_v3	ARM v3.
vARM_v7A	Cortex A architecture version.
vARM_v7R	Cortex R architecture version.
vARM_v7M	Cortex M3 architecture version.
vARM_v6M	Cortex M0 and M1 architecture version.
vARM_v8A	As per ARM an A suffix means that core has VMSA (MMU present) Currently in winIDEA ARMv8A indicates AArch64 (and AArch32 but we assume AArch32 won't be used) capable core. So we use this info in m_wVariant to select AArch64 disassembler and 64bit core register set.
vARM_v8R	As per ARM an R suffix means that core has PMSA (MPU instead MMU) Currently in winIDEA ARMv8R indicates AArch32 only core (there is no clear statement that it can't be AArch64 capable). We use this info in m_wVariant to select ARMv7 disassembler and ARMv7 register set.

◆ ECPUFamily

enum CCPUInfo::ECPUFamily

Defines CPU Family IDs.

Enumerator
cpu_8051	8051 family
cpu_RISCV	RISCV family.
cpu_Xtensa	Tensilica Xtensa DSP.
cpu_ARC	ARC family.
cpu_x86	x86
cpu_PowerPC	PowerPC family.
cpu_ARM	ARM family.
cpu_V850	V850 family.
cpu_TPU	TPU.
cpu_TriCore	TriCore family.
cpu_GTM	GTM.
cpu_SPT	SPT.
cpu_Generic	generic CPU

◆ EFeature_RISCV

enum CCPUInfo::EFeature_RISCV

Defines RISCV features.

Enumerator
fRISCV_M	RISCV_M.

◆ EPowerPC

enum CCPUInfo::EPowerPC

Defines PowerPC variants.

Enumerator
vPowerPC_4xx	4xx

◆ ERISCV

enum CCPUInfo::ERISCV

Defines RISCV variants.

Enumerator
vRISCV_RV32I	RV32I.

◆ ETriCore

enum CCPUInfo::ETriCore

Defines Tricore variants.

Enumerator
vTriCore13	TriCore13.